DMP is a member of the Altera Design Services Network (DSN) program.
Altera Corration is a world-leading programmable logic solutions company that pioneered the world’s first reprogrammable logic device in 1983, and remains the industry leading technology supplier for FPGA, CPLD and ASIC solutions.
DMP is a member of Xilinx Alliance Program (XAP). Founded in 1984, Xilinx Inc. is the world’s leading provider of programmable logic solutions.
DMP is a General Member of the Intel Embedded Alliance. Through this alliance, we provide solutions that deliver comprehensive support for product design and development that features our graphics IP cores, in combination with Intel architecture.
DMP is a member of the R-Car Consortium of Renesas Electronics Corporation.
The Khronos Group™ is an industry consortium that promotes the development and deployment of open standard graphics related APIs. As a Contributor Member, DMP actively participates in the process of establishing API specifications, such as OpenGL® ES and OpenVG™, and complies our products to these standards.
DMP is a member of EVA (Embedded Vision Alliance).
EVA is a claboration founded in 2011 to enable the rapid growth of computer vision features in embedded systems.
DMP is a member of the TSMC IP Alliance Program. Founded in 1987, TSMC is the largest pure IC foundry in the world.
DMP is a member of the HSA Foundation, which was founded in June 2012 as an initiative of AMD. The goal is to create and promote an open standard that combines the CPU and GPU as a unified processing engine.
OCP International Partnership Association, Inc. (OCP-IP) is a semiconductor industry consortium formed to administer the support, promotion, and enhancement of the Open Core Protocol (OCP). OCP is the openly licensed and comprehensive interface socket for semiconductor intellectual property (IP) cores, adopted as a standard bus protocol for SoCs on a wide variety of systems. DMP’s graphics IP cores support OCP, allowing our customers to improve mutual connectivity between IP cores, as well as reduce the risks and costs associated with the SoC design process.